1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a method of manufacturing a semiconductor device with interconnection contacts, which are formed by perpendicularly penetrating an insulating layer disposed between interconnections such as bit lines and to a device formed thereby.
2. Description of the Related Art
As semiconductor devices become more highly integrated, design rules are being scaled down. In particular, the contact size of DRAMs is decreasing with a higher integration density of semiconductor devices. However, to manufacture semiconductor devices, misalignment margin must be held at a certain level in a photolithography process. For this reason, forming reliable interconnection contacts becomes more complicated. In the sub-0.14 μm-regime, it becomes more difficult to form interconnection contacts, which penetrate gaps between interconnections such as bit lines, to be sufficiently insulated from the bit lines. To solve problems of interconnection contacts, for example, a short between a buried contact (BC) and a bit line, a variety of techniques were proposed. For example, a method of forming interconnection contacts using a self-aligned contact (SAC) process has proposed. Nevertheless, these new techniques require additional process steps and result in a big increase in loading capacitance between bit lines. The big increase in loading capacitance may degrade characteristics of semiconductor devices seriously and thus must be preferably suppressed.
The big increase in loading capacitance occurs due to, for example, silicon nitride spacers, which are formed on sides of bit lines when the SAC process is adopted. Since silicon nitride has a much higher dielectric constant than silicon oxide, which is typically used to insulate semiconductor devices, it allows loading capacitance to greatly increase. While it is possible to replace silicon nitride spacers with silicon oxide spacers, if this is done, it is difficult to obtain a desired profile. This also makes it difficult to secure a sufficient distance for electric insulation between bit lines and interconnection contacts.
The increase in loading capacitance, a reduced design rule and a much higher height of a stack of bit lines can cause serious problems. As the height of the stack of bit lines increases, the aspect ratio between the bit lines becomes larger and larger. Thus, if spacers are formed on sides of the bit lines so as to perform an SAC process, it becomes more difficult to fill gaps in an interlayer dielectric formed to insulate bit lines.